1. Field of the Invention
The present invention generally relates to a semiconductor package, and more particularly, to a semiconductor package having a Ball Grid Array structure.
This application relies for priority on Japanese patent application, Serial Number 234614/1998, filed Aug. 20, 1998, which is incorporated herein by reference in its entirety.
2. Description of the Related Art
An example of a conventional semiconductor device using a BGA (Ball Grid Array) structure is shown in FIG. 1. As shown in FIG. 1, a semiconductor device 40 (i.e., semiconductor package) is made up of a printed circuit board 14, a semiconductor element 16 (e.g., a semiconductor chip) and a resin 13.
The printed circuit board 14 has printed wirings formed on both front and back surfaces thereof and solder balls 12 which are arrayed along all sides of the printed circuit board 14 and are electrically connected to the wirings of the back surface of the printed circuit board 14. The semiconductor element 16 is placed on the front surface of the printed circuit board 14 so that a front surface 16a thereof on which circuits are formed faces upward. The semiconductor element 16 is electrically connected to wirings formed on the printed circuit board 14 through bonding wires 18 made of gold. The resin 13 protects the semiconductor element 16, bonding wires 18, and connection areas where the bonding wires 18 are connected to the wirings formed on the printed circuit board 14 from an external environment.
Another conventional semiconductor device 42 which is intended to reduce a device thickness and size is shown in FIG. 2. In the semiconductor device 42, a semiconductor element 16 is placed on the front surface of a printed circuit board 14 so that a surface 16a on which circuits are formed faces downward. Electrodes formed on the semiconductor element 16 are connected to electrodes on the printed circuit board 14 through solder bumps 15. The space located between the surface 16a and the printed circuit board 14 is sealed by an insulating resin 13.
In recent years, there has been a strong demand to further miniaturize the semiconductor device. In the case of the semiconductor device 40 shown in FIG. 1, it is necessary to set the length of the bonding wire to a relatively long length to avoid the possibility where the bonding wire 18 is shorted to the semiconductor element 16 by physically contacting the edge of the semiconductor element 16. Therefore, it is also necessary to use a bonding wire which has a relatively high wire-bond loop profile to avoid imperfect contact or breaking of the wire. However, in such a technique, the relatively long bonding wire 18 causes the thickness of the resin 13 become greater than that of the printed circuit board 14 and thus the total thickness of the semiconductor device 40 increases. This means that it is difficult to reduce the size of the semiconductor device as a whole.
In the case of the semiconductor device 40 shown in FIG. 2, the size of the printed circuit board 14 can be set to nearly the same as that of the semiconductor element 16. However, since the bump electrodes, which are provided on the printed circuit board 14 or the semiconductor element 16, are used for connecting the printed circuit board 14 and the semiconductor element 16, this technique has an low manufacturing-efficiency and is less cost-effective when compared to the wire-bonding technique.
Consequently, there has been a need for an improved semiconductor device.
It is an object of the present invention is to provide a semiconductor package having a smaller size.
It is another object of the present invention is to provide a method of fabricating a semiconductor package that may be reduced in overall size.
It is another object of the present invention is to provide a semiconductor package that is well cost-effective to produce.
It is another object of the present invention is to provide a semiconductor package that has a high manufacturing-efficiency.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor package which includes a semiconductor chip having a major surface and first pads formed on the major surface. The semiconductor package also includes a package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces, (c) a pad forming region adjacent to and along the side surface, (d) second pads formed on the pad forming region, (e) external electrodes formed on the first major surface of the package substrate, wherein the second major surface of the package substrate is fixed to the major surface of the semiconductor chip, and wherein the external electrodes are electrically connected to the second pads. The semiconductor package further includes bonding wires electrically connecting the first pads to the second pads and a sealing material covering the bonding wires and first and second pads.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims, and the accompanying drawings.